Embodiments of the present invention relate to a delay compensated continuous time comparator for integrated circuit applications.
Continuous time comparators are used to indicate when one input signal is equal to another input signal. However, because of the delay through the comparator, this equality is indicated by the comparator output signal after the condition has passed. This produces an error in signal comparison where the continuous time comparator is employed. Referring to FIG. 1, there is a diagram of a continuous time comparator of the prior art. FIG. 2 is a diagram showing inherent error of the comparator of FIG. 1, where the horizontal axis is time and the vertical axis is voltage. The comparator output signal Vcomp is initially low. Reference voltage Vref is relatively constant and is applied to the negative input of the comparator. Input signal Vin is applied to the positive input of the comparator. As Vin exceeds Vref the comparator output signal Vcomp goes from low to high. This transition occurs when input signal Vin is equal to reference voltage Vref+Td*dVin/dt, where Td is the delay time of the comparator and dVin/dt is the time derivative or slope of Vin when it is equal to Vref. Thus, the low-to-high transition is delayed with respect to the actual crossing time by delay time Td. In addition, at the time of the Vcomp transition Vin is greater than Vref by error voltage Verr. Thus, the continuous time comparator of the prior art produces errors in time and in voltage.
FIG. 3 is a simulation of a typical comparator of the prior art showing voltage and timing errors, where the horizontal axis is time and the vertical axis is voltage. The comparator output signal Vcomp in the lower diagram is initially low. Reference voltage Vref in the upper diagram is relatively constant at 1.35 V and is applied to the negative input of the comparator. Input voltage Vin is applied to the positive input of the comparator as in FIG. 1. The comparator output signal Vcomp begins a low-to-high transition at 350 ns as Vin approaches Vref. Vin crosses Vref at 375 ns, but Vcomp is not detected until 386 ns when it reaches 0.9 V. By this time, however, the Td error delay is 11.32 ns and the Verr error voltage is 41 mV.
In view of the foregoing problems, embodiments of the present invention are directed to voltage and timing errors in a continuous time comparator circuit.